{"id":364,"date":"2024-08-03T00:26:05","date_gmt":"2024-08-02T18:56:05","guid":{"rendered":"https:\/\/milieudigital.com\/?page_id=364"},"modified":"2024-08-05T09:38:56","modified_gmt":"2024-08-05T04:08:56","slug":"team-expertise","status":"publish","type":"page","link":"https:\/\/milieudigital.com\/?page_id=364","title":{"rendered":"Team Expertise"},"content":{"rendered":"<p>[et_pb_section fb_built=&#8221;1&#8243; custom_padding_last_edited=&#8221;on|desktop&#8221; next_background_color=&#8221;#ffffff&#8221; admin_label=&#8221;Header&#8221; _builder_version=&#8221;4.27.0&#8243; background_color=&#8221;#00B7F9&#8243; background_image=&#8221;https:\/\/milieudigital.com\/wp-content\/uploads\/2024\/07\/marketing-bg6.png&#8221; parallax=&#8221;on&#8221; custom_padding=&#8221;7vw||10vw||false|false&#8221; custom_padding_tablet=&#8221;100px||100px||true&#8221; custom_padding_phone=&#8221;||||true&#8221; bottom_divider_style=&#8221;ramp2&#8243; bottom_divider_height=&#8221;250px&#8221; bottom_divider_flip=&#8221;horizontal&#8221; bottom_divider_height_tablet=&#8221;150px&#8221; bottom_divider_height_phone=&#8221;110px&#8221; bottom_divider_height_last_edited=&#8221;on|phone&#8221; saved_tabs=&#8221;all&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_row _builder_version=&#8221;4.16&#8243; global_colors_info=&#8221;{}&#8221;][et_pb_column type=&#8221;4_4&#8243; _builder_version=&#8221;4.16&#8243; custom_padding=&#8221;|||&#8221; global_colors_info=&#8221;{}&#8221; custom_padding__hover=&#8221;|||&#8221;][et_pb_text _builder_version=&#8221;4.27.0&#8243; text_font=&#8221;Roboto||||||||&#8221; text_line_height=&#8221;1.8em&#8221; header_font=&#8221;Roboto|700|||||||&#8221; header_text_align=&#8221;center&#8221; header_font_size=&#8221;80px&#8221; header_line_height=&#8221;1.2em&#8221; header_3_font=&#8221;Roboto|700||on|||||&#8221; header_3_text_align=&#8221;center&#8221; header_3_text_color=&#8221;#ffffff&#8221; header_3_font_size=&#8221;24px&#8221; header_3_letter_spacing=&#8221;10px&#8221; header_3_line_height=&#8221;2em&#8221; text_orientation=&#8221;center&#8221; background_layout=&#8221;dark&#8221; module_alignment=&#8221;center&#8221; text_font_size_last_edited=&#8221;off|desktop&#8221; header_font_size_tablet=&#8221;&#8221; header_font_size_phone=&#8221;32px&#8221; header_font_size_last_edited=&#8221;on|phone&#8221; header_3_font_size_tablet=&#8221;16px&#8221; header_3_font_size_phone=&#8221;14px&#8221; header_3_letter_spacing_tablet=&#8221;5px&#8221; header_3_letter_spacing_phone=&#8221;&#8221; header_3_letter_spacing_last_edited=&#8221;on|tablet&#8221; global_colors_info=&#8221;{}&#8221;]<\/p>\n<h3>Domain knowledge + tools<\/h3>\n<h1><span style=\"color: #ffffff;\">Team Expertise<\/span><\/h1>\n<p>[\/et_pb_text][\/et_pb_column][\/et_pb_row][\/et_pb_section][et_pb_section fb_built=&#8221;1&#8243; admin_label=&#8221;Projects&#8221; _builder_version=&#8221;4.16&#8243; custom_margin=&#8221;|||&#8221; custom_padding=&#8221;80px||80px||true|false&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_row column_structure=&#8221;1_3,2_3&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; box_shadow_style=&#8221;preset1&#8243; global_colors_info=&#8221;{}&#8221;][et_pb_column type=&#8221;1_3&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_blurb title=&#8221;Design Verification&#8221; use_icon=&#8221;on&#8221; font_icon=&#8221;&#xf084;||fa||900&#8243; icon_alignment=&#8221;center&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; header_text_align=&#8221;center&#8221; global_colors_info=&#8221;{}&#8221;][\/et_pb_blurb][\/et_pb_column][et_pb_column type=&#8221;2_3&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_accordion _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; custom_margin=&#8221;|15px||15px|false|false&#8221; custom_padding=&#8221;|15px||15px|false|false&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_accordion_item title=&#8221;Domain Knowledge&#8221; open=&#8221;off&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;]<\/p>\n<ul>\n<li>DV team with an array of expertise<\/li>\n<li>Domain Expertise in Communication,<\/li>\n<li>Multimedia, Memory etc.<\/li>\n<li>Expertise on IP, Subsystem, ASIC and SoC Level<\/li>\n<li>Methodologies Expertise \u2013 e RM, OVM, UVM<\/li>\n<li>Language Expertise \u2013 VHDL, Verilog, SV, E, C, C++<\/li>\n<li>Verification of complex design like 5 G Modem, CPU,DSP<\/li>\n<li>PCIe, SONET, Encryption, IPv4, IPv6 and Ethernet Design Verification<\/li>\n<li>USB 2.0\/3.0 (Including HUB)<\/li>\n<li>Expertise in MIPI\/NOC (Router Design) \u2013 Low Power Design<br \/>Audio &amp; Video IP Verification (Algorithm based IP\u2019s)<\/li>\n<li>VIP Development per customer specification<\/li>\n<li>Gate Level and Power Aware Simulations<\/li>\n<\/ul>\n<p>[\/et_pb_accordion_item][et_pb_accordion_item title=&#8221;DV Tools&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221; open=&#8221;on&#8221;]<\/p>\n<ul>\n<li>Synopsys (VCS, VManager)<\/li>\n<li>Cadence (IUS, IES Simulators, Specman)<\/li>\n<li>Mentor Graphics (QuestaSim)<\/li>\n<li>Debug Tools: Verdi<\/li>\n<\/ul>\n<p>[\/et_pb_accordion_item][\/et_pb_accordion][\/et_pb_column][\/et_pb_row][et_pb_row _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_column type=&#8221;4_4&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_divider color=&#8221;#00B7F9&#8243; divider_style=&#8221;dashed&#8221; divider_position=&#8221;center&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; custom_margin=&#8221;0px||0px||false|false&#8221; custom_padding=&#8221;0px||0px||false|false&#8221; global_colors_info=&#8221;{}&#8221;][\/et_pb_divider][\/et_pb_column][\/et_pb_row][et_pb_row column_structure=&#8221;1_3,2_3&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; box_shadow_style=&#8221;preset1&#8243; global_colors_info=&#8221;{}&#8221;][et_pb_column type=&#8221;1_3&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_blurb title=&#8221;DFT&#8221; use_icon=&#8221;on&#8221; font_icon=&#8221;&#xf83e;||fa||900&#8243; icon_alignment=&#8221;center&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; header_text_align=&#8221;center&#8221; global_colors_info=&#8221;{}&#8221;][\/et_pb_blurb][\/et_pb_column][et_pb_column type=&#8221;2_3&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_accordion _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; custom_margin=&#8221;|15px||15px|false|false&#8221; custom_padding=&#8221;|15px||15px|false|false&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_accordion_item title=&#8221;Domain Knowledge&#8221; open=&#8221;off&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;]<\/p>\n<ul>\n<li>Dependent, Independent and partitioned blocks<\/li>\n<li>Memory BIST implementation<\/li>\n<li>Scan insertion at top level<\/li>\n<li>DRC Clean up at SOC level<\/li>\n<li>Scan inserted &amp; compression netlist generation<\/li>\n<li>EDT RTL generation and synthetization of EDT Logic<\/li>\n<li>Compression and EDT bypass mode<\/li>\n<li>JTAG and Boundary Scan<\/li>\n<li>Chain tracing and blockage<\/li>\n<li>Pattern generation (ATPG) for different fault models like SAF, TDF,<\/li>\n<li>Path delay, Small delay, IDDQ<\/li>\n<li>Pattern Re-targeting at block level and merging with top level<\/li>\n<li>Coverage Analysis and Improvement<br \/>OCC Insertion<\/li>\n<li>Test Points and Cut point insertion<\/li>\n<li>Validation of patterns with zero delay and SDF timing<\/li>\n<li>Simulation mismatches<br \/>Block level and Top-Level Mapping<\/li>\n<\/ul>\n<p>[\/et_pb_accordion_item][et_pb_accordion_item title=&#8221;DFT Tools&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221; open=&#8221;on&#8221;]<\/p>\n<ul>\n<li>Synopsys \u2013 DC Compiler, DFT Max,<\/li>\n<li>TetraMax, VCS<\/li>\n<li>Cadence \u2013 RC, Modus, NCSim<\/li>\n<li>Languages \u201c TCL, Perl, Unix &amp; Linux<\/li>\n<\/ul>\n<p>[\/et_pb_accordion_item][\/et_pb_accordion][\/et_pb_column][\/et_pb_row][et_pb_row _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_column type=&#8221;4_4&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_divider color=&#8221;#00B7F9&#8243; divider_style=&#8221;dashed&#8221; divider_position=&#8221;center&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; custom_margin=&#8221;0px||0px||false|false&#8221; custom_padding=&#8221;0px||0px||false|false&#8221; global_colors_info=&#8221;{}&#8221;][\/et_pb_divider][\/et_pb_column][\/et_pb_row][et_pb_row column_structure=&#8221;1_3,2_3&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; box_shadow_style=&#8221;preset1&#8243; global_colors_info=&#8221;{}&#8221;][et_pb_column type=&#8221;1_3&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_blurb title=&#8221;Analog Layout&#8221; use_icon=&#8221;on&#8221; font_icon=&#8221;&#xe109;||divi||400&#8243; icon_alignment=&#8221;center&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; header_text_align=&#8221;center&#8221; global_colors_info=&#8221;{}&#8221;][\/et_pb_blurb][\/et_pb_column][et_pb_column type=&#8221;2_3&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_accordion _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; custom_margin=&#8221;|15px||15px|false|false&#8221; custom_padding=&#8221;|15px||15px|false|false&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_accordion_item title=&#8221;Domain Knowledge&#8221; open=&#8221;off&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;]<\/p>\n<ul>\n<li>AMS\/RF layout-design<\/li>\n<li>CMOS Fundamentals, IC-Fabrication &amp;amp; Circuit-basics<\/li>\n<li>Layout-Flow &amp;amp; various Reliability Issues modules like PLL, Data-Converters &amp;amp; PMIC blocks<\/li>\n<li>EDA tools like Virtuoso LE\/XL, Assura, PVS, Calibre<\/li>\n<li>Deep Sub-Micron\/FinFET \/ Bi-CMOS technologies<\/li>\n<li>Independently execute layout design of the assigned Analog &amp; and; Mixed-Signal \/ RF blocks either at Onsite or Off-shore, which includes floor- planning as per area &amp; and top-level, parasiticaware routing &amp; amp; doing various required physical verifications.<\/li>\n<\/ul>\n<p>[\/et_pb_accordion_item][et_pb_accordion_item title=&#8221;Analog Layout Tools&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221; open=&#8221;on&#8221;]<\/p>\n<ul>\n<li>Virtuoso\/ICC2\/Calibre\/PERC<\/li>\n<li>EDA Software: Altium<\/li>\n<li>IC Design Software: Cadence Virtuoso<\/li>\n<li>ADIsimPLL\u2122<\/li>\n<\/ul>\n<p>[\/et_pb_accordion_item][\/et_pb_accordion][\/et_pb_column][\/et_pb_row][et_pb_row _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_column type=&#8221;4_4&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_divider color=&#8221;#00B7F9&#8243; divider_style=&#8221;dashed&#8221; divider_position=&#8221;center&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; custom_margin=&#8221;0px||0px||false|false&#8221; custom_padding=&#8221;0px||0px||false|false&#8221; global_colors_info=&#8221;{}&#8221;][\/et_pb_divider][\/et_pb_column][\/et_pb_row][et_pb_row column_structure=&#8221;1_3,2_3&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; box_shadow_style=&#8221;preset1&#8243; global_colors_info=&#8221;{}&#8221;][et_pb_column type=&#8221;1_3&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_blurb title=&#8221;Design &#038; Embedded&#8221; use_icon=&#8221;on&#8221; font_icon=&#8221;&#xf2db;||fa||900&#8243; icon_alignment=&#8221;center&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; header_text_align=&#8221;center&#8221; global_colors_info=&#8221;{}&#8221;][\/et_pb_blurb][\/et_pb_column][et_pb_column type=&#8221;2_3&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_accordion _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; custom_margin=&#8221;|15px||15px|false|false&#8221; custom_padding=&#8221;|15px||15px|false|false&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_accordion_item title=&#8221;Hardware engineering&#8221; open=&#8221;off&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;]<\/p>\n<ul>\n<li>Board Design<\/li>\n<li>Circuit Design<\/li>\n<li>Circuit Analysis<\/li>\n<li>PCB Design<\/li>\n<li>Programmable Logic Design<\/li>\n<li>Prototyping (FPGA\/CPLD)<\/li>\n<li>Mechanical CAD and Analysis<\/li>\n<\/ul>\n<p>[\/et_pb_accordion_item][et_pb_accordion_item title=&#8221;Embedded software&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221; open=&#8221;on&#8221;]<\/p>\n<ul>\n<li>Bare Metal Firmware Development<\/li>\n<li>Firmware development using RTOS<\/li>\n<li>Expertise in Bootloaders\/BIOS such as UEFI, Core Boot, Uboot<\/li>\n<li>OS customization\/kernel customization<\/li>\n<li>Device Drivers for Linux and RTOS platforms<\/li>\n<\/ul>\n<p>[\/et_pb_accordion_item][\/et_pb_accordion][\/et_pb_column][\/et_pb_row][et_pb_row _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_column type=&#8221;4_4&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_divider color=&#8221;#00B7F9&#8243; divider_style=&#8221;dashed&#8221; divider_position=&#8221;center&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; custom_margin=&#8221;0px||0px||false|false&#8221; custom_padding=&#8221;0px||0px||false|false&#8221; global_colors_info=&#8221;{}&#8221;][\/et_pb_divider][\/et_pb_column][\/et_pb_row][et_pb_row column_structure=&#8221;1_3,2_3&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; box_shadow_style=&#8221;preset1&#8243; global_colors_info=&#8221;{}&#8221;][et_pb_column type=&#8221;1_3&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_blurb title=&#8221;VLSI Offerings&#8221; use_icon=&#8221;on&#8221; font_icon=&#8221;&#xf31e;||fa||900&#8243; icon_alignment=&#8221;center&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; header_text_align=&#8221;center&#8221; global_colors_info=&#8221;{}&#8221;][\/et_pb_blurb][\/et_pb_column][et_pb_column type=&#8221;2_3&#8243; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_accordion _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; custom_margin=&#8221;|15px||15px|false|false&#8221; custom_padding=&#8221;|15px||15px|false|false&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_accordion_item title=&#8221;ASIC Design (RTL)&#8221; open=&#8221;on&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;]<\/p>\n<ul>\n<li>Architecture Exploration<\/li>\n<li>Modeling<\/li>\n<li>(Reference \/ Behavioral)<\/li>\n<li>Micro-Architecture Development<\/li>\n<li>RTL Design &amp; Integration<\/li>\n<li>DFT Implementation<\/li>\n<li>Synthesis &amp; Static Timing Analysis<br \/>lint(Spyglass), CDC<\/li>\n<li>Low power, UPF, LEC<\/li>\n<\/ul>\n<p>[\/et_pb_accordion_item][et_pb_accordion_item title=&#8221;Verification (DV)&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221; open=&#8221;off&#8221;]<\/p>\n<ul>\n<li>Verification. Env Architecture Development<\/li>\n<li>IP \/ Block \/SOC Level Verification<\/li>\n<li>SOC Level, CPU, GLS, C Based<\/li>\n<li>Formal \/ Assertion based Verification<\/li>\n<li>Emulation &amp; FPGA Verification<\/li>\n<li>VIP Development\n<\/li>\n<\/ul>\n<p>[\/et_pb_accordion_item][et_pb_accordion_item title=&#8221;DFT&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221; open=&#8221;off&#8221;]<\/p>\n<ul>\n<li>Gate Level (RTL)<\/li>\n<li>SOC-DFT Implementation and Integration<\/li>\n<li>ATPG, ATPG-DRC clean-up, Pattern<\/li>\n<li>Generation, fault models, coverage analysis and improvement<\/li>\n<li>Synopsys DC, DFTC, DFTMAX, Tetramax<\/li>\n<li>Verification and debug VCS, Simvision, NC-Verilog, Questa<\/li>\n<li>BIST, MBIST Architect, SMS<\/li>\n<li>Shell scripting, Verilog, Tcl, and\/or Perl\/Python<\/li>\n<\/ul>\n<p>[\/et_pb_accordion_item][et_pb_accordion_item title=&#8221;Circuit &#038; Layout Design&#8221; _builder_version=&#8221;4.27.0&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221; open=&#8221;off&#8221;]<\/p>\n<ul>\n<li>Analog\/IO\/RF\/Digital\/ AMS Circuit Design<\/li>\n<li>Behavioral\/Spice\/ IBIS Modeling<br \/>Characterization<\/li>\n<li>Layout: Analog\/IO\/Memory\/ RF&amp;MS<\/li>\n<li>Complete Library Development<br \/>Technology Migration<\/li>\n<\/ul>\n<p>[\/et_pb_accordion_item][\/et_pb_accordion][\/et_pb_column][\/et_pb_row][\/et_pb_section][et_pb_section fb_built=&#8221;1&#8243; custom_padding_last_edited=&#8221;on|desktop&#8221; prev_background_color=&#8221;#ffffff&#8221; admin_label=&#8221;Call to action&#8221; _builder_version=&#8221;4.27.0&#8243; background_color=&#8221;#02ccfe&#8221; background_image=&#8221;https:\/\/milieudigital.com\/wp-content\/uploads\/2024\/07\/marketing-bg6.png&#8221; parallax=&#8221;on&#8221; custom_padding=&#8221;16vw||7vw||false|false&#8221; custom_padding_tablet=&#8221;100px||100px||true&#8221; custom_padding_phone=&#8221;||||true&#8221; top_divider_style=&#8221;ramp2&#8243; top_divider_height=&#8221;250px&#8221; top_divider_flip=&#8221;vertical&#8221; top_divider_height_tablet=&#8221;150px&#8221; top_divider_height_phone=&#8221;110px&#8221; top_divider_height_last_edited=&#8221;on|phone&#8221; global_module=&#8221;174&#8243; saved_tabs=&#8221;all&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_row module_class=&#8221; et_pb_row_fullwidth&#8221; _builder_version=&#8221;4.16&#8243; width=&#8221;89%&#8221; width_tablet=&#8221;80%&#8221; width_phone=&#8221;80%&#8221; width_last_edited=&#8221;on|desktop&#8221; max_width=&#8221;89%&#8221; max_width_tablet=&#8221;80%&#8221; max_width_phone=&#8221;80%&#8221; max_width_last_edited=&#8221;on|desktop&#8221; custom_margin_phone=&#8221;|||&#8221; custom_margin_last_edited=&#8221;off|desktop&#8221; custom_padding=&#8221;|||&#8221; make_fullwidth=&#8221;on&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_column type=&#8221;4_4&#8243; _builder_version=&#8221;4.16&#8243; custom_padding=&#8221;|||&#8221; global_colors_info=&#8221;{}&#8221; custom_padding__hover=&#8221;|||&#8221;][et_pb_text _builder_version=&#8221;4.16&#8243; text_font=&#8221;||||||||&#8221; header_font=&#8221;||||||||&#8221; header_2_font=&#8221;Roboto|700|||||||&#8221; header_2_line_height=&#8221;1.4em&#8221; header_3_font=&#8221;Roboto|700||on|||||&#8221; header_3_text_align=&#8221;center&#8221; header_3_text_color=&#8221;#ffffff&#8221; header_3_font_size=&#8221;24px&#8221; header_3_letter_spacing=&#8221;5px&#8221; header_3_line_height=&#8221;2em&#8221; text_orientation=&#8221;center&#8221; background_layout=&#8221;dark&#8221; max_width=&#8221;850px&#8221; module_alignment=&#8221;center&#8221; custom_margin=&#8221;|||&#8221; custom_padding=&#8221;|||&#8221; text_font_size_last_edited=&#8221;off|desktop&#8221; header_2_font_size_tablet=&#8221;40px&#8221; header_2_font_size_phone=&#8221;32px&#8221; header_2_font_size_last_edited=&#8221;on|desktop&#8221; header_3_font_size_tablet=&#8221;16px&#8221; header_3_font_size_phone=&#8221;14px&#8221; global_colors_info=&#8221;{}&#8221;]<\/p>\n<h3>Let\u2019s Get Started<\/h3>\n<h2><span style=\"color: #ffffff;\">Ready To Make a Real Change? Let&#8217;s Build this Thing Together!<\/span><\/h2>\n<p>[\/et_pb_text][et_pb_button button_url=&#8221;@ET-DC@eyJkeW5hbWljIjp0cnVlLCJjb250ZW50IjoicG9zdF9saW5rX3VybF9wYWdlIiwic2V0dGluZ3MiOnsicG9zdF9pZCI6IjI1MSJ9fQ==@&#8221; button_text=&#8221;Setup a Meeting&#8221; button_alignment=&#8221;center&#8221; _builder_version=&#8221;4.27.0&#8243; _dynamic_attributes=&#8221;button_url&#8221; custom_button=&#8221;off&#8221; button_bg_use_color_gradient=&#8221;on&#8221; button_bg_color_gradient_direction=&#8221;90deg&#8221; button_bg_color_gradient_stops=&#8221;#f92c8b 0%|#b02cd6 100%&#8221; button_bg_color_gradient_start=&#8221;#f92c8b&#8221; button_bg_color_gradient_end=&#8221;#b02cd6&#8243; background_layout=&#8221;dark&#8221; custom_margin=&#8221;|||&#8221; custom_padding=&#8221;18px|34px|18px|34px|true|true&#8221; box_shadow_style=&#8221;preset3&#8243; box_shadow_vertical=&#8221;20px&#8221; box_shadow_blur=&#8221;30px&#8221; box_shadow_spread=&#8221;-10px&#8221; box_shadow_color=&#8221;rgba(249,44,139,0.4)&#8221; button_letter_spacing_hover=&#8221;5.5px&#8221; global_colors_info=&#8221;{}&#8221; button_text_size__hover_enabled=&#8221;off&#8221; button_one_text_size__hover_enabled=&#8221;off&#8221; button_two_text_size__hover_enabled=&#8221;off&#8221; button_text_color__hover_enabled=&#8221;off&#8221; button_one_text_color__hover_enabled=&#8221;off&#8221; button_two_text_color__hover_enabled=&#8221;off&#8221; button_border_width__hover_enabled=&#8221;off&#8221; button_one_border_width__hover_enabled=&#8221;off&#8221; button_two_border_width__hover_enabled=&#8221;off&#8221; button_border_color__hover_enabled=&#8221;off&#8221; button_one_border_color__hover_enabled=&#8221;off&#8221; button_two_border_color__hover_enabled=&#8221;off&#8221; button_border_radius__hover_enabled=&#8221;off&#8221; button_one_border_radius__hover_enabled=&#8221;off&#8221; button_two_border_radius__hover_enabled=&#8221;off&#8221; button_letter_spacing__hover_enabled=&#8221;on&#8221; button_letter_spacing__hover=&#8221;5.5px&#8221; button_one_letter_spacing__hover_enabled=&#8221;off&#8221; button_two_letter_spacing__hover_enabled=&#8221;off&#8221; button_bg_color__hover_enabled=&#8221;off&#8221; button_one_bg_color__hover_enabled=&#8221;off&#8221; button_two_bg_color__hover_enabled=&#8221;off&#8221;][\/et_pb_button][\/et_pb_column][\/et_pb_row][\/et_pb_section]<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Domain knowledge + tools Team Expertise DV team with an array of expertise Domain Expertise in Communication, Multimedia, Memory etc. Expertise on IP, Subsystem, ASIC and SoC Level Methodologies Expertise \u2013 e RM, OVM, UVM Language Expertise \u2013 VHDL, Verilog, SV, E, C, C++ Verification of complex design like 5 G Modem, CPU,DSP PCIe, SONET, [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_et_pb_use_builder":"on","_et_pb_old_content":"","_et_gb_content_width":"","footnotes":""},"class_list":["post-364","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/milieudigital.com\/index.php?rest_route=\/wp\/v2\/pages\/364","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/milieudigital.com\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/milieudigital.com\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/milieudigital.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/milieudigital.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=364"}],"version-history":[{"count":12,"href":"https:\/\/milieudigital.com\/index.php?rest_route=\/wp\/v2\/pages\/364\/revisions"}],"predecessor-version":[{"id":391,"href":"https:\/\/milieudigital.com\/index.php?rest_route=\/wp\/v2\/pages\/364\/revisions\/391"}],"wp:attachment":[{"href":"https:\/\/milieudigital.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=364"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}