Domain knowledge + tools
Team Expertise
Design Verification
Domain Knowledge
- DV team with an array of expertise
- Domain Expertise in Communication,
- Multimedia, Memory etc.
- Expertise on IP, Subsystem, ASIC and SoC Level
- Methodologies Expertise – e RM, OVM, UVM
- Language Expertise – VHDL, Verilog, SV, E, C, C++
- Verification of complex design like 5 G Modem, CPU,DSP
- PCIe, SONET, Encryption, IPv4, IPv6 and Ethernet Design Verification
- USB 2.0/3.0 (Including HUB)
- Expertise in MIPI/NOC (Router Design) – Low Power Design
Audio & Video IP Verification (Algorithm based IP’s) - VIP Development per customer specification
- Gate Level and Power Aware Simulations
DV Tools
- Synopsys (VCS, VManager)
- Cadence (IUS, IES Simulators, Specman)
- Mentor Graphics (QuestaSim)
- Debug Tools: Verdi
DFT
Domain Knowledge
- Dependent, Independent and partitioned blocks
- Memory BIST implementation
- Scan insertion at top level
- DRC Clean up at SOC level
- Scan inserted & compression netlist generation
- EDT RTL generation and synthetization of EDT Logic
- Compression and EDT bypass mode
- JTAG and Boundary Scan
- Chain tracing and blockage
- Pattern generation (ATPG) for different fault models like SAF, TDF,
- Path delay, Small delay, IDDQ
- Pattern Re-targeting at block level and merging with top level
- Coverage Analysis and Improvement
OCC Insertion - Test Points and Cut point insertion
- Validation of patterns with zero delay and SDF timing
- Simulation mismatches
Block level and Top-Level Mapping
DFT Tools
- Synopsys – DC Compiler, DFT Max,
- TetraMax, VCS
- Cadence – RC, Modus, NCSim
- Languages “ TCL, Perl, Unix & Linux
Analog Layout
Domain Knowledge
- AMS/RF layout-design
- CMOS Fundamentals, IC-Fabrication & Circuit-basics
- Layout-Flow & various Reliability Issues modules like PLL, Data-Converters & PMIC blocks
- EDA tools like Virtuoso LE/XL, Assura, PVS, Calibre
- Deep Sub-Micron/FinFET / Bi-CMOS technologies
- Independently execute layout design of the assigned Analog & and; Mixed-Signal / RF blocks either at Onsite or Off-shore, which includes floor- planning as per area & and top-level, parasiticaware routing & amp; doing various required physical verifications.
Analog Layout Tools
- Virtuoso/ICC2/Calibre/PERC
- EDA Software: Altium
- IC Design Software: Cadence Virtuoso
- ADIsimPLL™
Design & Embedded
Hardware engineering
- Board Design
- Circuit Design
- Circuit Analysis
- PCB Design
- Programmable Logic Design
- Prototyping (FPGA/CPLD)
- Mechanical CAD and Analysis
Embedded software
- Bare Metal Firmware Development
- Firmware development using RTOS
- Expertise in Bootloaders/BIOS such as UEFI, Core Boot, Uboot
- OS customization/kernel customization
- Device Drivers for Linux and RTOS platforms
VLSI Offerings
ASIC Design (RTL)
- Architecture Exploration
- Modeling
- (Reference / Behavioral)
- Micro-Architecture Development
- RTL Design & Integration
- DFT Implementation
- Synthesis & Static Timing Analysis
lint(Spyglass), CDC - Low power, UPF, LEC
Verification (DV)
- Verification. Env Architecture Development
- IP / Block /SOC Level Verification
- SOC Level, CPU, GLS, C Based
- Formal / Assertion based Verification
- Emulation & FPGA Verification
- VIP Development
DFT
- Gate Level (RTL)
- SOC-DFT Implementation and Integration
- ATPG, ATPG-DRC clean-up, Pattern
- Generation, fault models, coverage analysis and improvement
- Synopsys DC, DFTC, DFTMAX, Tetramax
- Verification and debug VCS, Simvision, NC-Verilog, Questa
- BIST, MBIST Architect, SMS
- Shell scripting, Verilog, Tcl, and/or Perl/Python
Circuit & Layout Design
- Analog/IO/RF/Digital/ AMS Circuit Design
- Behavioral/Spice/ IBIS Modeling
Characterization - Layout: Analog/IO/Memory/ RF&MS
- Complete Library Development
Technology Migration